1. Technical Field
Various embodiments of the present disclosure generally relate to semiconductor integrated circuits, and more particularly, to bit line precharge voltage generation circuits for semiconductor memory apparatuses.
2. Related Art
A semiconductor memory apparatus may transfer data stored in a memory cell to a bit line, amplify the data transferred to the bit line through a bit line sense amplifier, sequentially transfer the amplified data to a sub input/output line and a local input/output line, and output the data to the outside of the semiconductor memory apparatus.
FIG. 1 is a diagram illustrating a conventional semiconductor memory apparatus. A conventional semiconductor may include a first switching unit 10, a first precharge unit 20, a second switching unit 30, and a second precharge unit 40.
The first switching unit 10 may include first and second transistors N1 and N2. The first switching unit 10 may connect bit lines BL and BLb to sub input/output lines SIO and SIOb in response to a column select signal Yi.
The first precharge unit 20 may include third through fifth transistors N3 through N5. The first precharge unit 20 may precharge the sub input/output lines SIO and SIOb to a level of a bit line precharge voltage VBLP when a bit line equalization signal BLEQ is lowered to a low level.
The second switching unit 30 may include sixth and seventh transistors N6 and N7. The second switching unit 30 may connect the sub input/output lines SIO and SIOb to the local input/output lines LIO and LIOb when the bit line equalization signal BLEQ is raised is to a high level.
Second precharge unit 40 may include eighth through tenth transistors P1 through P3. Second precharge unit 40 may precharge the local input/output lines LIO and LIOb to a level of a core voltage Vcore. The level of the bit line precharge voltage VBLP may be half the level of the core voltage Vcore.
The semiconductor memory apparatus, illustrated in FIG. 1, may raise the bit line precharge voltage VBLP through repetitive refresh operations. A precharge operation may follow each refresh operation. Hence, the precharge operation may repeat along with the refresh operation.
As illustrated in FIG. 1, second precharge unit 40 may precharge the local input/output lines LIO and LIOb to the level of the core voltage Vcore, and the first precharge unit 20 may precharge the sub input/output lines SIO and SIOb to the level of the bit line precharge voltage VBLP. Meanwhile, when the precharge operation is not performed, the second switching unit 30 may connect the sub input/output lines SIO and SIOb to the local input/output lines LIO and LIOb, respectively. That is, when the bit line equalization signal BLEQ increases to a high level, the second switching unit 30 may connect the sub input/output lines SIO and SIOb to the local input/output lines LIO and LIOb, respectively. When the bit line equalization signal BLEQ is lowered to a low level, the first precharge unit 20 may precharge the sub input/output lines SIO and Slob.
As the refresh operation is repeated, the number of connections between the local input/output lines LIO and LIOb precharged to the level of the core voltage Vcore and the sub input/output lines SIO and SIOb precharged to the level of the bit line precharge voltage VBLP may increase. Therefore, the voltage levels of the precharged sub input/output lines SIO and SIOb may become higher than the level of the bit line precharge voltage VBLP, which may raise the level of the bit line precharge voltage VBLP. Specifically, the semiconductor memory apparatus may supply the bit line precharge voltage VBLP to the sub input/output lines SIO and SIOb when the sub input/output lines SIO and SIOb are precharged. However, the voltage levels of the sub input/output lines SIO and SIOb may be raised due to the repetitive refresh operations, and the voltages of the sub input/output lines SIO and SIOb may flow to a node where the bit line precharge voltage VBLP is applied. Thus, the level of the bit line precharge voltage VBLP may be raised.
When the bit line precharge voltage VBLP is raised, the precharge voltage level of the bit lines BL and BLb may be also raised. Therefore, when data of the memory cell is transferred to the bit lines BL and BLb, a voltage difference between the bit lines BL and BLb is less than a preset voltage difference. Hence, a bit line sense amplifier configured to sense and amplify the voltage levels of the bit lines BL and BLb may operate abnormally.